> When intel came out with it's first SIMD instruction set I was happy
to<br />&gt; try them on my application. It was a failure. Because even if
one<br />&gt; instruction executes on 3 data locations it's cost was 3 CPU
cycles. Three<br />&gt; integer instructions cost 1 cycle each. Also with
SIMD you had to load the<br />&gt; registers first. &lt;snip&gt;<br /><br
/>MMX and SSE were rather a disaster on this point.<br />Acually, I learn
to play with SIMD using Altivec on PowerPC and that's a complete different
deal. SSSE3 and upcoming SSE4 are ratehr good too.<br /><br />&gt; And,
Yes, optimizing at this level is a rare situation.<br />I will be curious
to know which kind of IP algorithm need those but this is maybe a topic
that should go private instead of adding noise to the list.