Re: [boost] platform specific structures

From: Matt Hurd (matt.hurd_at_[hidden])
Date: 2004-09-20 07:34:27

> On Mon, 20 Sep 2004 15:17:43 +0300, Peter Dimov <pdimov_at_[hidden]> wrote:
> 
> But why is a concurrent-aware setter useful if its effects aren't visible to
> the other threads?

In what way do you mean they not visible?

Such aligned memory operations are guaranteed to be atomic on ia32 at
a system wide level AFAIK.

Here is what Intel has to say:
______________________

7.1. LOCKED ATOMIC OPERATIONS

The 32-bit IA-32 processors support locked atomic operations on
locations in system memory.
These operations are typically used to manage shared data structures
(such as semaphores,
segment descriptors, system segments, or page tables) in which two or
more processors may try simultaneously to modify the same field or
flag. The processor uses three interdependent mechanisms for carrying
out locked atomic operations:
  • guaranteed atomic operations 
   ^^^^^^^^^^^^^^^^^^^
  • bus locking, using the LOCK# signal and the LOCK instruction prefix
  • cache coherency protocols that insure that atomic operations can
be carried out on cached
data structures (cache lock); this mechanism is present in the Pentium
4, Intel Xeon, and P6 family processors These mechanisms are
interdependent in the following ways. Certain basic memory
transactions (such as reading or writing a byte in system memory) are
always guaranteed to be handled atomically.

That is, once started, the processor guarantees that the operation
will be completed before
another processor or bus agent is allowed access to the memory
location. The processor also
supports bus locking for performing selected memory operations (such
as a read-modify-write
operation in a shared area of memory) that typically need to be
handled atomically, but are not
automatically handled this way. Because frequently used memory
locations are often cached in
a processor's L1 or L2 caches, atomic operations can often be carried
out inside a processor's
caches without asserting the bus lock. Here the processor's cache
coherency protocols insure
that other processors that are caching the same memory locations are
managed properly while
atomic operations are performed on cached memory locations.

Note that the mechanisms for handling locked atomic operations have
evolved as the complexity
of IA-32 processors has evolved. As such, more recent IA-32 processors
(such as the Pentium 4, Intel Xeon, and P6 family processors) provide
a more refined locking mechanism than earlier
IA-32 processors. These are described in the following sections.