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From: Alexander Terekhov (terekhov_at_[hidden])
Date: 2005-04-07 05:19:10


Peter Dimov wrote:
[...]
> > P.S. When are you going to kick start an incarnation for Itanic
> > with value dependent cmpxchg.rel-vs-cmpxchg.acq? ;-)
>
> IA64 assembly by hand? No thanks. I'll probably use _Interlocked* on Intel
> and __sync_* on g++.

That would mean expensive "mf" everywhere.

http://gcc.gnu.org/ml/libstdc++/2005-04/msg00059.html
http://gcc.gnu.org/ml/libstdc++/2005-04/msg00060.html

Not good for Itanic which reportedly speculates and reorders like
crazy.

  asm long atomic_decrement_weak( register long * pw ) {

    loop:

      <load-UNordered>
      <add -1>
      <branch if zero to acquire>
      <cmpxchg.rel>
      <branch if failed to loop else to done>
      
    acquire:

      <ld.acq>
      <add -1>
      <branch if !zero to acquire>

    done:

      <...>
  }

  asm long atomic_decrement_strong( register long * pw ) {

    loop:

      <load-UNordered>
      <add -1>
      <branch if zero to acquire>
      <cmpxchg.rel>
      <branch if failed to loop else to done>
      
    acquire:

      <cmpxchg.acq>
      <branch if failed to loop else to done>

    done:

      <...>

  }

Oder?

regards,
alexander.

P.S. For naked stuff, it is probably better to use ".rel", not
more-speculation-hindering ".acq". Too bad Itanic doesn't have
naked "semaphores"...


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