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From: Johan Råde (rade_at_[hidden])
Date: 2006-12-08 09:39:42

Boris Gubenko wrote:

> While only VMS supports multiple floating-point modes, conditionalization
> below will be correct for all the platforms the cxx compiler supports:
> #if defined(__DECCXX) && !__IEEE_FLOAT
> # VAX FP mode
> #endif

Then I should be able to add code that handles the VAX FP modes.

Do both platforms support uint64_t?

How is long double implemented in the VAX FP mode?
Is it the same as double, or does it have more than 8 bytes?

How does the sign bit work in the VAX FP mode?
Is it the leading bit of the leading byte?
Do you reverse the sign of a number simply by flipping the sign bit?

>>> Alpha
>>> ------
>>> float: -n.min/2 00 00 00 00
>>> double: -n.min/2 00 00 00 00 00 00 00 00
>> = positive zero
>>> IPF
>>> ---
>>> float: -n.min/2 80 00 00 00
>>> double: -n.min/2 80 00 00 00 00 00 00 00
>> = negative zero
> Does it represent a problem on either platform or this is
> implementation-defined?

For practical purposes it can't be a problem.
Positive and negative zero are really the same number.

I'm not an expert on floating point arithmetic and IEEE 754 standard,
so I can't give you a better answer than that.

> Based on the results I posted yesterday, is it correct to say that fpclassify
> library passes the tests on both VMS platforms?

That is correct. It has passed all tests on both VMS platforms,
in both full ieee mode and fast ieee mode.


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