Date: 2008-04-18 11:50:22
If the CAS is prefixed with 'lock' (intel) then this emits a two way
barrier. Virtually all compiler built ins of CAS do this. In my
implementation of queue I did not need barriers other than those already
used by the CAS.
I am interested in developing some lock-free libs for boost, if other
are willing to help. I have a working unbounded MS Queue (relies on DCAS
at the moment, but I have ideas on how to just support Single CAS (e.g.
the node allocator could always align on 64 byte boundaries, leaving
space for a counter with a reasonable range). I have a linearized
smart_ptr (which makes STM much much easier in C++). I have a
std::allocator --compatible lockfree allocator (reduced contention
inside of container quite a bit) and of course a stack.
[mailto:boost-bounces_at_[hidden]] On Behalf Of Patrick Twohig
Sent: Friday, April 18, 2008 11:32 AM
Subject: Re: [boost] Nonlocking data structures.
Another article talks about writing on the Xbox360, which is what I
needed a queue for:
On Fri, Apr 18, 2008 at 3:51 AM, Giovanni Piero Deretta
> On Fri, Apr 18, 2008 at 3:09 AM, Cory Nelson <phrosty_at_[hidden]>
> > On Thu, Apr 17, 2008 at 5:24 PM, Patrick Twohig <p-twohig_at_[hidden]>
> > > Theoretically, the CAS should atomically compare and swap the
> > value
> in one
> > > clock cycle. However, with multiple cores/processors/hyper
> threading where
> > > multiple instructions are being executed simultaneously over
> > > numbers of clock cycles. There can be writes pending while you
> > want
> to read
> > > from memory. As a result, when you go to read something another
> > > will have written to but you read stale data. To combat this,
> > you
> enforce a
> > > memory barrier, which guarantees that all pending memory
> transactions before
> > > the barrier have completed before moving on with the program.
> > > some architectures (like x86) allow for unaligned access of
> When an
> > > unaligned value is accessed, it sets an exception then it
> > replaces
> > > single read/write operation with multiple bus operations which
> wreaks havoc
> > > on any compare/swap operations.
> > They don't happen in a single cycle, I don't think there is
> > anything specifying that they should. Barriers aren't needed on
> > x86 or x64, other than compile-time only ones to make sure the
> > compiler doesn't reorder something.
> Well, you actually need StoreLoad memory barriers on x86. All other
> barriers are always implicit (unless you use non temporal SSE
> StoreLoad is also implicit if you use locked operations, otherwise you
> need an explicit mfence.
> See, for example, http://g.oswego.edu/dl/jmm/cookbook.html
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