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Subject: Re: [boost] [review] Dataflow Library
From: Michael Caisse (boost_at_[hidden])
Date: 2008-09-08 01:36:22

Phil Endecott wrote:
> Michael Caisse wrote:
>> I don't think I understand. Verilog supports dataflow modeling and
>> for anything
>> non-trivial is the main mode of modeling. What am I missing?
> In Verilog (or VHDL), if I have two components that I want to "pipe"
> together I need to declare a wire that will be the channel for the
> communication and then declare the two components with this wire
> connected to the appropriate port. Something like this:
> wire[7:0] a;
> ExampleSource src (.the_output(a));
> ExampleSink sink (.the_input(a));
> As far as I am aware, neither language has syntax to pipe them
> together more concisely, i.e.
> ExampleSource src >>= ExampleSink sink;

Maybe I need some educating. It wouldn't be the first time (o; . I thought Dataflow programming
dealt primarily with the fact that components have inputs and outputs. These inputs/outputs are
connected to other components. Components "execute" once the required inputs are available.
Is there a definition that requires the connection to be defined by a pipe like construct or
can the binding be a wire? I'm not sure that the binding description is important.

For my own work I describe the components and then describe the bindings. I think of it as
wiring up the outputs and inputs (which can of course fan-out). Eventually I get a directed graph.

I guess this sounds a lot like the Verilog Data Flow abstraction to me. I assume
I am still missing something.

> Please do! As soon as some people who actually know something about
> Dataflow start posting comments then I will shut up. My comments are
> intended really just to provoke debate.
> Regards, Phil.

Debate is good.

Best Regard-

Michael Caisse
Object Modeling Designs

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