Re: [boost] boost.atomic and boost.lockfree backports

Subject: Re: [boost] boost.atomic and boost.lockfree backports
From: Tim Blechmann (tim_at_[hidden])
Date: 2011-05-29 06:29:34

>>* boost.atomic: 128bit lockfree atomics for MSVC 2008+ (using
>>_InterlockedCompareExchange128 and SSE2 intrinsics) and GCC-compatible
>> POSIX compilers (using 16 byte __sync intrinsics). This code is x86-64
>> specific, and disabled by default. Define BOOST_ATOMIC_HAVE_SSE2 to enable
>> in x86-64 MSVC 2008+ environments. Define BOOST_ATOMIC_HAVE_SSE2,
> 
> ... atomics and sse2? how does this work together? afair, sse2 reads/writes
> are not even guaranteed to be atomic and both concepts are quite orthogonal
> ...

double-checked with intel's software developer's manual, volume 3a, section 
8.1.1: there is no way to access 128bit words atomically. afaik, the only way to 
implement them correctly is to use cmpxchg16b ... 

-- 
tim_at_[hidden]
http://tim.klingt.org
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  John Cage quoting Jasper Johns