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Subject: Re: [boost] Boost SIMD beta release
From: Mathias Gaunard (mathias.gaunard_at_[hidden])
Date: 2012-12-25 10:52:24

On 25/12/12 16:28, Peter Dimov wrote:
> Mathias Gaunard wrote:
>> On 25/12/12 15:43, Peter Dimov wrote:
>> > Mathias Gaunard wrote:
>> >> The shifted iterator and the shifted load allow to do aligned loads if
>> >> you statically know the misalignment of the memory.
>> >
>> > Does this have any performance advantage over just using an unaligned
>> > load? I'd expect the microcode to do whatever the shifted load does,
>> but
>> > I haven't measured it.
>> The shifted load statically knows the alignment, unaligned loads do not.
>> Note that the switch is outside of the loop, not for each load.
> Ah, you're probably talking AltiVec, which probably doesn't have an
> unaligned load instruction. I was thinking SSE, which does.

I'm not talking of any ISA in particular.
Not all instructions have the same latency and bandwidth.

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