Subject: Re: [Boost-bugs] [Boost C++ Libraries] #3341: sp_counted_base_gcc_sparc.hpp compile failure on gcc.4.2.3 w/-O2
From: Boost C++ Libraries (noreply_at_[hidden])
Date: 2009-08-15 18:14:40
#3341: sp_counted_base_gcc_sparc.hpp compile failure on gcc.4.2.3 w/-O2
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Reporter: jon_p_griffiths@⦠| Owner: pdimov
Type: Bugs | Status: new
Milestone: Boost 1.40.0 | Component: smart_ptr
Version: Boost 1.39.0 | Severity: Problem
Keywords: gcc, CAS, sp_counted_base |
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Comment(by jon_p_griffiths@â¦):
> the proper constraint could be 'V' instead of 'm'.
I tried +V before reporting but it also failed (with 'inconsistent asm
contraints' IIRC). I found two sparc CAS implementations by googling
(GASNet and the Linux kernel) - both use the following formulation:
{{{
__asm__ __volatile("cas [%2], %3, %0\n\t"
: "=&r" (swap_)
: "0" (swap_), "r" (dest_), "r" (compare_)
: "memory");
}}}
This forces the address to be stored in a register, which avoids any
offset addition in the emitted instruction. However, the Linux kernel
implementation adds memory barriers before and after the CAS; it would be
interesting to know whether they are really needed in this case.
For reference, I've tested the following version; it seems to be running
without issues here:
{{{
inline int32_t compare_and_swap( volatile int32_t * dest_, int32_t
compare_, int32_t swap_ )
{
__asm__ __volatile__("membar #StoreLoad|#LoadLoad\n"
"cas [%2], %3, %0\n"
"membar #StoreLoad|#StoreStore\n"
: "=&r" (swap_)
: "0" (swap_), "r" (dest_), "r" (compare_)
: "memory");
return swap_;
}
}}}
Cheers,
Jon
-- Ticket URL: <https://svn.boost.org/trac/boost/ticket/3341#comment:2> Boost C++ Libraries <http://www.boost.org/> Boost provides free peer-reviewed portable C++ source libraries.
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