Re: [jamboost] chipsets (architectures and instructions) was: more variants

From: Reece Dunn (msclrhd_at_[hidden])
Date: 2004-07-20 11:10:37

Vladimir Prus wrote:
>Hi Alexander,
> > But how can I force different directories for linux/sun and 32/64bit?
>
>I think for 32/64 thing, the right approach is to improve the toolsets. 
>Just
>add
>
> feature address-mode : 32 64 : propagated ;
>
>to builtin jam and lines like
>
> flags gcc.compile OPTIONS <address-mode>64 : -the-right-switch ;
>
>to gcc.jam and sun.jam. As soon as you get it working, send a patch and 
>I'll
>include this in CVS.

It would be beneficial to select the compiler used for different 
architectures/chipsets. For example, Microsoft provide a cross-compiler for 
the IA-64 architecture in the PlatformSDK directory (the Feb 2003 version is 
13.10.2240.8). Also, the Metrowerks codewarrior compiler supports x86, 68k 
and PowerPC chips using different compiler/linker names (you can also add a 
parameter to the cwenv.bat program to configure the right includes and 
libraries).

There are also several different processors for each target IA-32 (Pentium; 
PentiumPro; P2; P3; P4; Athalon); IA-64 (Itanium; Itanium2; Athalon64). Each 
of these have support for different instructions (MMX; SSE; SSE2; 3d Now!).

Compilers can optimize for these different architectures and instruction 
sets. The Microsoft compilers 6.0 - 7.1 support the /Gn flags:

6.0 - /G5 [Pentium]; /G6 [PentiumPro]
7.0 - /G5 [Pentium]; /G6 [PentiumPro; P2; P3]
7.1 - /G5 [Pentium]; /G6 [PentiumPro; P2; P3]; /G7 [P4; Athalon]
7.1 IA64 - /G1 [Itanium]; /G2 [Itanium2]

Microsoft compiler version 8 does not support /Gn, but does have /arch:SSE 
and /arch:SSE2 flags!

Borland 5.5 provides the -5 flag for Pentium and -6 for PentiumPro chips.

CodeWarrior (x86) provides the following:
-proc [Pentium : PPro : PII : PIII : AMDK6 : Athalon]
-inst [mmx : sse : 3dnow]

NOTE: Intel P2 supports MMX instructions; P3 supports MMX and SSE 
instructions; and P4 supports MMX, SSE and SSE2 instructions.

It should be possible to deduce the instruction sets from the chipsets. The 
question is, how to group the chipsets:

IA-32 (x86) -- Pentium; PentiumPro; P2; P3; P4; Athalon
IA-64 -- Itanium; Itanium2; Athalon64
68k -- m68k

The chipsets will imply an addressing model.

Thoughts? Comments?

Regards,
Reece

_________________________________________________________________
Want to block unwanted pop-ups? Download the free MSN Toolbar now! 
http://toolbar.msn.co.uk/