[Boost-commit] svn:boost r62174 - sandbox/gtl/doc

Subject: [Boost-commit] svn:boost r62174 - sandbox/gtl/doc
From: lucanus.j.simonson_at_[hidden]
Date: 2010-05-24 13:03:37

Author: ljsimons
Date: 2010-05-24 13:03:36 EDT (Mon, 24 May 2010)
New Revision: 62174
URL: http://svn.boost.org/trac/boost/changeset/62174

Log:
fix for diode misinformation and clarification of layout
Text files modified: 
   sandbox/gtl/doc/gtl_tutorial.htm |    12 ++++++------                            
   1 files changed, 6 insertions(+), 6 deletions(-)

Modified: sandbox/gtl/doc/gtl_tutorial.htm
==============================================================================
--- sandbox/gtl/doc/gtl_tutorial.htm	(original)
+++ sandbox/gtl/doc/gtl_tutorial.htm	2010-05-24 13:03:36 EDT (Mon, 24 May 2010)
@@ -67,10 +67,7 @@
 family with four transistors.  The NAND gate has two inputs and one output.  
 Each input goes to two transistors, one p-type transistor and one n-type 
 transistor.  The "p" stands for positive and the "n" stands for negative.  
-A p-type transistor behaves like a diode (allows voltage and current to pass 
-forward but not reverse) between the voltage source and the output when it is 
-switched on in digital operation.  The n-type transistor behaves like a 
-diode between the output and the ground.  When the p-type transistor is on 
+When the p-type transistor is on 
 it pulls the output up to the same voltage as the voltage source.  When the 
 n-type transistor is on it pulls the output down to the same voltage as the 
 ground.  The process of creating a p-type transistor begins by "doping" the silicon 
@@ -106,10 +103,13 @@
 output of the gate will be a logical "true" because the transistor will connect 
 it to the voltage supply.  The diagram below is an example of how a NAND 
 gate might be laid out and is not drawn to scale for any real process 
-technology.</p>
+technology.&nbsp; The diffusion material is intended to be cut away under the 
+gate material by a Boolean NOT operation and is represented as solid bars under 
+the gates of transistors only for convenience of drawing.</p>
 <p>
 <img border="0" src="images/NAND.PNG" width="602" height="387"></p>
-<p>The following is the input layout file for the above NAND gate layout:</p>
+<p>The following is the input layout file for the above NAND gate layout, 
+rectangle format is XL XH YL YH:</p>
 <p><font face="Courier New" size="2">Rectangle 0 60 24 48 NWELL<br>
 Rectangle 3 57 32 43 PDIFF<br>
 Rectangle 3 57 5 16 NDIFF<br>