[Boost-commit] svn:boost r82156 - trunk/boost/atomic/detail

Subject: [Boost-commit] svn:boost r82156 - trunk/boost/atomic/detail
From: andrey.semashev_at_[hidden]
Date: 2012-12-21 16:01:20

Author: andysem
Date: 2012-12-21 16:01:19 EST (Fri, 21 Dec 2012)
New Revision: 82156
URL: http://svn.boost.org/trac/boost/changeset/82156

Log:
Restored full fence in the platform_fence_after_load function on architectures other than x86 and x86_64. The fence is not required only on those architectures.
Text files modified: 
   trunk/boost/atomic/detail/windows.hpp |    18 +++++++++++++-----                      
   1 files changed, 13 insertions(+), 5 deletions(-)

Modified: trunk/boost/atomic/detail/windows.hpp
==============================================================================
--- trunk/boost/atomic/detail/windows.hpp	(original)
+++ trunk/boost/atomic/detail/windows.hpp	2012-12-21 16:01:19 EST (Fri, 21 Dec 2012)
@@ -42,7 +42,7 @@
 #pragma intrinsic(_mm_mfence)
 #endif
 
-BOOST_FORCEINLINE void x86_full_fence(void)
+BOOST_FORCEINLINE void hardware_full_fence(void)
 {
 #if defined(_MSC_VER) && (defined(_M_AMD64) || (defined(_M_IX86) && defined(_M_IX86_FP) && _M_IX86_FP >= 2))
     // Use mfence only if SSE2 is available
@@ -55,12 +55,9 @@
 
 // Define compiler barriers
 #if defined(_MSC_VER) && _MSC_VER >= 1310 && !defined(_WIN32_WCE)
-
 extern "C" void _ReadWriteBarrier();
 #pragma intrinsic(_ReadWriteBarrier)
-
 #define BOOST_ATOMIC_READ_WRITE_BARRIER() _ReadWriteBarrier()
-
 #endif
 
 #ifndef BOOST_ATOMIC_READ_WRITE_BARRIER
@@ -95,6 +92,17 @@
 platform_fence_after_load(memory_order order)
 {
     BOOST_ATOMIC_READ_WRITE_BARRIER();
+
+    // On x86 and x86_64 there is no need for a hardware barrier,
+    // even if seq_cst memory order is requested, because all
+    // seq_cst writes are implemented with lock-prefixed operations
+    // or xchg which has implied lock prefix. Therefore normal loads
+    // are already ordered with seq_cst stores on these architectures.
+
+#if !(defined(_MSC_VER) && (defined(_M_AMD64) || defined(_M_IX86)))
+    if (order == memory_order_seq_cst)
+        hardware_full_fence();
+#endif
 }
 
 } // namespace detail
@@ -106,7 +114,7 @@
 {
     BOOST_ATOMIC_READ_WRITE_BARRIER();
     if (order == memory_order_seq_cst)
-        atomics::detail::x86_full_fence();
+        atomics::detail::hardware_full_fence();
 }
 
 #define BOOST_ATOMIC_SIGNAL_FENCE 2