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Boost-Commit : |
Subject: [Boost-commit] svn:boost r85586 - trunk/boost/atomic/detail
From: andrey.semashev_at_[hidden]
Date: 2013-09-06 13:37:29
Author: andysem
Date: 2013-09-06 13:37:29 EDT (Fri, 06 Sep 2013)
New Revision: 85586
URL: http://svn.boost.org/trac/boost/changeset/85586
Log:
Added macro checks for more ARM targets. The macros were taken from smart_ptr/detail/spinlock_gcc_arm.hpp.
Text files modified:
trunk/boost/atomic/detail/gcc-armv6plus.hpp | 79 ++++++++++++++++++++-------------------
trunk/boost/atomic/detail/platform.hpp | 5 ++
2 files changed, 45 insertions(+), 39 deletions(-)
Modified: trunk/boost/atomic/detail/gcc-armv6plus.hpp
==============================================================================
--- trunk/boost/atomic/detail/gcc-armv6plus.hpp Fri Sep 6 11:43:07 2013 (r85585)
+++ trunk/boost/atomic/detail/gcc-armv6plus.hpp 2013-09-06 13:37:29 EDT (Fri, 06 Sep 2013) (r85586)
@@ -66,29 +66,27 @@
// to annotate the conditional instructions. These are ignored in other modes (e.g. v6),
// so they can always be present.
-#if defined(__thumb__) && !defined(__ARM_ARCH_7A__)
-// FIXME also other v7 variants.
+#if defined(__thumb__) && !defined(__thumb2__)
#define BOOST_ATOMIC_ARM_ASM_START(TMPREG) "adr " #TMPREG ", 1f\n" "bx " #TMPREG "\n" ".arm\n" ".align 4\n" "1: "
#define BOOST_ATOMIC_ARM_ASM_END(TMPREG) "adr " #TMPREG ", 1f + 1\n" "bx " #TMPREG "\n" ".thumb\n" ".align 2\n" "1: "
-
#else
// The tmpreg is wasted in this case, which is non-optimal.
#define BOOST_ATOMIC_ARM_ASM_START(TMPREG)
#define BOOST_ATOMIC_ARM_ASM_END(TMPREG)
#endif
-#if defined(__ARM_ARCH_7A__)
-// FIXME ditto.
+#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_7S__)
#define BOOST_ATOMIC_ARM_DMB "dmb\n"
#else
#define BOOST_ATOMIC_ARM_DMB "mcr\tp15, 0, r0, c7, c10, 5\n"
#endif
inline void
-arm_barrier(void)
+arm_barrier(void) BOOST_NOEXCEPT
{
int brtmp;
- __asm__ __volatile__ (
+ __asm__ __volatile__
+ (
BOOST_ATOMIC_ARM_ASM_START(%0)
BOOST_ATOMIC_ARM_DMB
BOOST_ATOMIC_ARM_ASM_END(%0)
@@ -97,56 +95,59 @@
}
inline void
-platform_fence_before(memory_order order)
+platform_fence_before(memory_order order) BOOST_NOEXCEPT
{
- switch(order) {
- case memory_order_release:
- case memory_order_acq_rel:
- case memory_order_seq_cst:
- arm_barrier();
- case memory_order_consume:
- default:;
+ switch(order)
+ {
+ case memory_order_release:
+ case memory_order_acq_rel:
+ case memory_order_seq_cst:
+ arm_barrier();
+ case memory_order_consume:
+ default:;
}
}
inline void
-platform_fence_after(memory_order order)
+platform_fence_after(memory_order order) BOOST_NOEXCEPT
{
- switch(order) {
- case memory_order_acquire:
- case memory_order_acq_rel:
- case memory_order_seq_cst:
- arm_barrier();
- default:;
+ switch(order)
+ {
+ case memory_order_acquire:
+ case memory_order_acq_rel:
+ case memory_order_seq_cst:
+ arm_barrier();
+ default:;
}
}
inline void
-platform_fence_before_store(memory_order order)
+platform_fence_before_store(memory_order order) BOOST_NOEXCEPT
{
platform_fence_before(order);
}
inline void
-platform_fence_after_store(memory_order order)
+platform_fence_after_store(memory_order order) BOOST_NOEXCEPT
{
if (order == memory_order_seq_cst)
arm_barrier();
}
inline void
-platform_fence_after_load(memory_order order)
+platform_fence_after_load(memory_order order) BOOST_NOEXCEPT
{
platform_fence_after(order);
}
template<typename T>
inline bool
-platform_cmpxchg32(T & expected, T desired, volatile T * ptr)
+platform_cmpxchg32(T & expected, T desired, volatile T * ptr) BOOST_NOEXCEPT
{
int success;
int tmp;
- __asm__ (
+ __asm__ __volatile__
+ (
BOOST_ATOMIC_ARM_ASM_START(%2)
"mov %1, #0\n" // success = 0
"ldrex %0, %3\n" // expected' = *(&i)
@@ -163,7 +164,7 @@
: "r" (expected), // %4
"r" (desired) // %5
: "cc"
- );
+ );
return success;
}
@@ -174,13 +175,14 @@
inline void
atomic_thread_fence(memory_order order)
{
- switch(order) {
- case memory_order_acquire:
- case memory_order_release:
- case memory_order_acq_rel:
- case memory_order_seq_cst:
- atomics::detail::arm_barrier();
- default:;
+ switch(order)
+ {
+ case memory_order_acquire:
+ case memory_order_release:
+ case memory_order_acq_rel:
+ case memory_order_seq_cst:
+ atomics::detail::arm_barrier();
+ default:;
}
}
@@ -194,9 +196,8 @@
class atomic_flag
{
private:
- atomic_flag(const atomic_flag &) /* = delete */ ;
- atomic_flag & operator=(const atomic_flag &) /* = delete */ ;
uint32_t v_;
+
public:
BOOST_CONSTEXPR atomic_flag(void) BOOST_NOEXCEPT : v_(0) {}
@@ -220,6 +221,9 @@
atomics::detail::platform_fence_after(order);
return expected;
}
+
+ BOOST_DELETED_FUNCTION(atomic_flag(const atomic_flag &))
+ BOOST_DELETED_FUNCTION(atomic_flag& operator=(const atomic_flag &))
};
#define BOOST_ATOMIC_FLAG_LOCK_FREE 2
@@ -249,4 +253,3 @@
#endif /* !defined(BOOST_ATOMIC_FORCE_FALLBACK) */
#endif
-
Modified: trunk/boost/atomic/detail/platform.hpp
==============================================================================
--- trunk/boost/atomic/detail/platform.hpp Fri Sep 6 11:43:07 2013 (r85585)
+++ trunk/boost/atomic/detail/platform.hpp 2013-09-06 13:37:29 EDT (Fri, 06 Sep 2013) (r85586)
@@ -38,7 +38,10 @@
// I don't know how complete it is.
#elif defined(__GNUC__) && (defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \
|| defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \
- || defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_7A__))
+ || defined(__ARM_ARCH_6K__) \
+ || defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \
+ || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \
+ || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_7S__))
#include <boost/atomic/detail/gcc-armv6plus.hpp>
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