Re: [Boost-users] Support for sp_counted_base for HP Itanium aCC compiler

From: Baruch Zilber (baruchz_at_[hidden])
Date: 2007-07-25 02:52:27

>Hi Baruch,

> 

>thank you for doing this.

> 

>Can you, please, post your code here (I guess, it is a header file like

>sp_counted_base_gcc_ia64.hpp)?. It will be reviewed by the Boost
community

>and we'll review it at HP. And, then, it can be added to Boost,
hopefully,

>in Boost 1.35 time frame.

> 

>Thanks again,

>  Boris

 

I copy the file sp_counted_base_gcc_ia64.hpp to
sp_counted_base_acc_ia64.hpp and change the following methods:

atomic_increment(),atomic_decrement() and atomic_conditional_increment()

 

The change was:

 

#include <machine/sys/inline.h>

 

inline void atomic_increment( int * pw )

{

    _Asm_mf();

    static_cast<int>(_Asm_fetchadd(_FASZ_W, _SEM_REL, (void*)pw, +1,
_LDHINT_NONE) + 1);

} 

 

inline int atomic_decrement( int * pw )

{

    _Asm_mf();

    return (static_cast<int>(_Asm_fetchadd(_FASZ_W, _SEM_REL, (void*)pw,
-1, _LDHINT_NONE) - 1) - 1);

}

 

inline int atomic_conditional_increment( int * pw )

{

    return _Asm_mov_to_ar((_Asm_app_reg)_AREG_CCV,

                          *pw,

                          (_Asm_fence)(_UP_CALL_FENCE | _UP_SYS_FENCE |
_DOWN_CALL_FENCE | _DOWN_SYS_FENCE)),

                         _Asm_mf(), 

                         (_Asm_cmpxchg((_Asm_sz)4,

                                       (_Asm_sem)_SEM_REL, 

                                        pw,

                                        *pw + 1,

                         (_Asm_ldhint)_LDHINT_NONE));

}

 

Thanks

Baruch

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