Re: [boost] [atomic, x86] need another pair of eyes

Subject: Re: [boost] [atomic, x86] need another pair of eyes
From: Tim Blechmann (tim_at_[hidden])
Date: 2012-12-19 06:34:38

hi andrey and peter,

to be more specific: of the test machines at sandia sometimes has test
failures for boost.lockfree, which i cannot reproduce on my machine. the
algorithm in question (the spsc_queue) only makes use of atomic reads
and writes and only requires two memory barriers. the sandia machine is
a 4 cpu, 8 core/cpu machine, while my machines are all single-cpu
multi-core.

peter, the compare_exchange is in boost/atomic/detail/gcc-x86.hpp, the
code in question looks like:

    bool
    compare_exchange_strong(
        value_type & expected,
        value_type desired,
        memory_order success_order,
        memory_order failure_order) volatile
    {
        value_type previous = expected;
        platform_fence_before(success_order);
        __asm__ (
            "lock ; cmpxchgl %2, %1"
            : "+a" (previous), "+m" (v_)
            : "r" (desired)
        );
        bool success = (previous == expected);
        if (success)
            platform_fence_after(success_order);
        else
            platform_fence_after(failure_order);
        expected = previous;
        return success;
    }

imo, the platform_fence_before/after is not necessary ...

tim