Re: [boost] [atomic, x86] need another pair of eyes

Subject: Re: [boost] [atomic, x86] need another pair of eyes
From: Andrey Semashev (andrey.semashev_at_[hidden])
Date: 2012-12-19 06:35:54

On Wed, Dec 19, 2012 at 3:27 PM, Peter Dimov <lists_at_[hidden]> wrote:
> Andrey Semashev wrote:
>
>> On x86 memory view is almost always synchronized (AFAIK, the only
>> exception is non-temporal stores, which are usually finalized with
>> explicit mfence anyway), so unless the user requests
>> memory_order_seq_cst only compiler barrier will suffice. As for
>> memory_order_seq_cst, it requires global sequencing, and here's the
>> part I'm not sure about. Lock-prefixed ops on x86 are full fences
>> themselves, so it looks like no special hardware fence is needed in
>> this case either. So unless I'm missing something, mfence could be
>> removed as well in this case. Could somebody confirm that?
>
>
> Where (file/line) is the mfence that can be removed?

atomic/detail/windows.hpp, line 174.

Comparing it to gcc-x86.hpp, the gcc implementation indeed doesn't
have it, so I'm probably right.