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From: Philippe A. Bouchard (philippeb_at_[hidden])
Date: 2003-11-18 01:51:50

Alexander Terekhov wrote:
> "Philippe A. Bouchard" wrote:
> [...]
>> Obviously the smart pointer will need to run on SPARC servers for
> SPARC-RMO ("vaporware", AFAIK) and also "the" POWER (IBM) do have
> naked atomics and "disjoint" (with respect to atomics) load and
> store barriers (in various combination)... but, unfortunately, they
> are bidirectional load/store "fences" (that's way too heavy; for
> efficiency, you really need "hoist-only"/"sink-only" semantics in
> most cases), IIUC.

Ha ha ha... I guess I should of mentionned the Alpha with its 2 pipelines

>> multithreaded environments. It looked like shared_count_x86_exp2.cpp
>> coudn't run on multiple platforms.
> Yeah. refcount<> (and compilers with not-rocket-science knowledge
> of atomics with "hoist" and "sink" barriers... and that's no matter
> how screwed is the hardware -- compilers may reorder "as well") is
> the way to go. I guess.

Before going further with those issues I would like to specify that most of
the time we do not need to know the content of the integer; we only need to
know whether it is null or not atomically... the machine instructions "dec
[counter]" immediately followed by "jne" do that. It is too bad portable
assembly code is nearly impossible: N compilers * M processors. It would be
great for the generated code of "int volatile counter; if (-- counter) ...;"
to get atomic and standardized eventually... some sort of huge helper ;)



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