[boost] [atomic, x86] need another pair of eyes

Subject: [boost] [atomic, x86] need another pair of eyes
From: Tim Blechmann (tim_at_[hidden])
Date: 2012-12-19 05:36:55

hi all,

i need another pair of eyes regarding boost.atomic on x86:

the implementation of memory barrier is merely a compiler barrier, but
not a CPU barrier, as it is using code like:
__asm__ __volatile__ ("" ::: "memory");

afaict, one should use a `real' CPU barrier like "mfence" or "lock; addl
$0,0(%%esp)". is this correct?

apart from that, i've seen that compare_exchange is using explicit
memory barriers before/after "cmpxchg" instructions. i somehow though
that cmpxchg and the 8b/16b variants implicitly issue a memory barrier,
so the resulting code would generate multiple memory barriers.

can someone with some insights in the x86 architecture confirm this?

thanks, tim