From: Reece Dunn (msclrhd_at_[hidden])
Date: 2005-10-20 05:24:14
Vladimir Prus <ghost <at> cs.msu.su> writes:
> On Wednesday 19 October 2005 19:33, Alexey Pakhunov wrote:
> > Reece Dunn wrote:
> > > + # sh
> > > + sh3 sh3dsp sh4 sh5
> > Can these shXxx be expressed via combinations of <architecture>sh and
> > different <address-model> and <instruction-set>?
> Good question. Anybody has a semi-formal definition of <architecture> and
> <instruction-set> features?
<architecture> specifies the general CPU type being used. That is, what
architectural design is being used on the chip. For example, x86 specifies the
Intel X86 based CPUs such as Pentium 4.
<instruction-set> specifies what CPU/assembler instructions are available for
the given architecture. For example, using the instructions available with the
AMD Athalon CPU.
> I'm not quite sure how they mix together,
> especially for power and mips architectures, that have a huge number of
> instructions sets.
I am not sure either. Especially, it is not clear what instruction sets
(CPU type?) map to mips2 and what map to mips4.
To me, instruction set indicates something like:
but then I may want to add more instruction sets for MMX, SSE, SSE2 or AMD
instruction sets. Having <instruction-set> specify the CPU type gives implied
instruction sets, e.g.:
pentium4 ==> MMX + SSE + SSE2
As for the power, mips, sh and arm architectures, I do not have an understanding
of how these are structured. It would be useful if these were documented
(especially mips2/..., etc.).
Also, what if you have:
It would be nice if we could do something like:
feature instruction-set : <architecture>x86 : pentium pentium2 ... ;
feature instruction-set : <architecture>mips2 : ... ;
which would allow bjam to report an error for the above mips4/pentium example
and would make what instruction sets are associated with which architectures
I am not sure how this would be implemented with BBv2, but it should be easier
with BBpy :).
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