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Subject: Re: [Boost-users] shared_ptr and weak_ptr concurrency
From: John Dlugosz (JDlugosz_at_[hidden])
Date: 2009-09-08 11:37:32


> Just to make sure I understand, am I right that this assumes x86/x64
> CPUs and only those built in types up to register size (no 64 bit
> integers) and may not include single bytes in all circumstances?

Right, no 64-bit integers under x86; only native register sizes. Single bytes might include bool types, but (in theory) a volatile value won't have such shenanigans on it.

>
> If you wrote code that depended on this assumption how could you be
> sure
> it wouldn't be ported to a box with a different CPU (I move stuff all
> the time between x86 and AIX, HPUX and sometimes a VAX).

I encapsulate my thread stuff as tightly as possible. So in free code I should be making assumptions about atomicness of assignment; only that the assignment operator on my type is correctly written if documented to be atomic.

So, don't allow that assumption to spill out into the program at large. Your queue or message or update or whatever will be encapsulated into a class that may use such tricks, and it can be altered if necessary for each platform.

Document the class, including the thread guarantees.

Put strict #ifdef's in the class, to ensure it is only used on the platform you tested it on. If the same code works on more than one, add to the #if when you vet it.

For the other platforms, check the documentation, or experts using them. The details of the whole toolset of lock-free (and special atomic instruction free) programming will differ, but some things may be universal across them, like certain types (native register size) that are read and written atomically.

> Can I make the same assumptions or not? And how can I be sure?

> Thanks,
>
> Jerry
>

Check the manual for that CPU, examine existing code that works on it, and write your own test code. For example, I make use of a "trick" that is not strictly allowed in the CPU manual, but works fine. My test program validates that, and it is run on each successive CPU generation to make sure it still works.

--John

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