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From: Anthony Williams (anthony_w.geo_at_[hidden])
Date: 2007-03-23 12:20:48

"Peter Dimov" <pdimov_at_[hidden]> writes:

> On x86 all loads already have acquire semantics by default, and all stores
> have release semantics.

Not according to the intel specs. 25366818.pdf (IA32 software developers
manual volume 3A), section 7.7.2:

"1. Reads can be carried out speculatively and in any order."

This means that loads cannot have acquire semantics as they can be reordered
with respect to other reads. You need a fence or other serializing instruction
to stop this reordering.

This only happens on P4, Xeon and P6 processors --- Pentium and 486 CPUs don't
do out-of-order reads.

> MSVC 8.0 extends a volatile load/store to have
> acquire/release semantics (both hardware and compiler) on every platform,
> including IA64.

I agree that's what it says, but it doesn't put any serializing instructions
in. Unless Intel have given Microsoft better guarantees than they've published
in their specs, then that doesn't help.


Anthony Williams
Just Software Solutions Ltd -
Registered in England, Company Number 5478976.
Registered Office: 15 Carrallack Mews, St Just, Cornwall, TR19 7UL

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