Boost logo

Boost :

From: Peter Dimov (pdimov_at_[hidden])
Date: 2007-03-23 12:53:46

Anthony Williams wrote:
> "Peter Dimov" <pdimov_at_[hidden]> writes:
>> On x86 all loads already have acquire semantics by default, and all
>> stores have release semantics.
> Not according to the intel specs. 25366818.pdf (IA32 software
> developers manual volume 3A), section 7.7.2:
> "1. Reads can be carried out speculatively and in any order."
> This means that loads cannot have acquire semantics as they can be
> reordered with respect to other reads. You need a fence or other
> serializing instruction to stop this reordering.
> This only happens on P4, Xeon and P6 processors --- Pentium and 486
> CPUs don't do out-of-order reads.

Physical reads are carried out speculatively and out of order, but they
still have acquire semantics from the program's point of view. The CPU has a
unit that watches for load-acquire violations and discards the speculatively
read value if such a violation is detected. This is a recurring topic in
c.p.t and comp.arch, I believe, mostly because the Intel and AMD specs
aren't clear. Alexander likes to cite the IA64 specs where it is stated that
ld.acq and st.rel produce the equivalent of the x86 memory model.

Boost list run by bdawes at, gregod at, cpdaniel at, john at